Commit 0bc3c1ec authored by Lovis J.I. Zenz's avatar Lovis J.I. Zenz
Browse files

Merge branch 'armtranslation' into 'develop'

Armtranslation

See merge request !1
parents 50a958a6 9e24aaa2
Pipeline #1410 passed with stage
in 2 minutes and 6 seconds
......@@ -145,12 +145,12 @@ in
| MLA x: conditional sem-mla x
| MLS x: conditional sem-mls x
| MUL x: conditional sem-mul x
# | SMLABB x: conditional sem-smlabb x
# | SMLABT x: conditional sem-smlabt x
# | SMLATB x: conditional sem-smlatb x
# | SMLATT x: conditional sem-smlatt x
# | SMLAD x: conditional sem-smlad x
# | SMLADX x: conditional sem-smladx x
| SMLABB x: conditional sem-smlabb x
| SMLABT x: conditional sem-smlabt x
| SMLATB x: conditional sem-smlatb x
| SMLATT x: conditional sem-smlatt x
| SMLAD x: conditional sem-smlad x
| SMLADX x: conditional sem-smlad x
| SMLAL x: conditional sem-smlal x
# | SMLALBB x: conditional sem-smlalbb x
# | SMLALBT x: conditional sem-smlalbt x
......@@ -1375,6 +1375,166 @@ val sem-mul x = do
emit-flags-nz (var result) x.o
end
val sem-smlabb x = do
rd <- lval x.opnd1;
opnd1 <- rval x.opnd4;
opnd2 <- rval x.opnd3;
ra <- rval x.opnd2;
factor1 <- mktemp;
factor2 <- mktemp;
result <- mktemp;
addend <- mktemp;
comparator <- mktemp;
movsx 32 factor1 16 opnd1;
movsx 32 factor2 16 opnd2;
mul 32 result (var factor1) (var factor2);
movsx 64 result 32 (var result);
movsx 64 addend 32 ra;
add 64 result (var result) (var addend);
mov 32 rd (var result);
movsx 64 comparator 32 (var rd);
cmpneq 64 fQF (var result) (var comparator)
end
val sem-smlabt x = do
rd <- lval x.opnd1;
opnd1 <- lval x.opnd4;
opnd2 <- rval x.opnd3;
ra <- rval x.opnd2;
factor1 <- mktemp;
factor2 <- mktemp;
result <- mktemp;
addend <- mktemp;
comparator <- mktemp;
movsx 32 factor1 16 (var (at-offset opnd1 16));
movsx 32 factor2 16 opnd2;
mul 32 result (var factor1) (var factor2);
movsx 64 result 32 (var result);
movsx 64 addend 32 ra;
add 64 result (var result) (var addend);
mov 32 rd (var result);
movsx 64 comparator 32 (var rd);
cmpneq 64 fQF (var result) (var comparator)
end
val sem-smlatb x = do
rd <- lval x.opnd1;
opnd1 <- rval x.opnd4;
opnd2 <- lval x.opnd3;
ra <- rval x.opnd2;
factor1 <- mktemp;
factor2 <- mktemp;
result <- mktemp;
addend <- mktemp;
comparator <- mktemp;
movsx 32 factor1 16 opnd1;
movsx 32 factor2 16 (var (at-offset opnd2 16));
mul 32 result (var factor1) (var factor2);
movsx 64 result 32 (var result);
movsx 64 addend 32 ra;
add 64 result (var result) (var addend);
mov 32 rd (var result);
movsx 64 comparator 32 (var rd);
cmpneq 64 fQF (var result) (var comparator)
end
val sem-smlatt x = do
rd <- lval x.opnd1;
opnd1 <- lval x.opnd4;
opnd2 <- lval x.opnd3;
ra <- rval x.opnd2;
factor1 <- mktemp;
factor2 <- mktemp;
result <- mktemp;
addend <- mktemp;
comparator <- mktemp;
movsx 32 factor1 16 (var (at-offset opnd1 16));
movsx 32 factor2 16 (var (at-offset opnd2 16));
mul 32 result (var factor1) (var factor2);
movsx 64 result 32 (var result);
movsx 64 addend 32 ra;
add 64 result (var result) (var addend);
mov 32 rd (var result);
movsx 64 comparator 32 (var rd);
cmpneq 64 fQF (var result) (var comparator)
end
val sem-smlad x = do
rd <- lval x.opnd1;
opnd2 <- lval x.opnd3;
rn <- lval x.opnd4;
ra <- rval x.opnd2;
factor11 <- mktemp;
factor12 <- mktemp;
factor21 <- mktemp;
factor22 <- mktemp;
product1 <- mktemp;
product2 <- mktemp;
addend <- mktemp;
result <- mktemp;
comparator <- mktemp;
movsx 32 factor11 16 (var rn);
movsx 32 factor12 16 (var (at-offset rn 16));
movsx 32 factor21 16 (var opnd2);
movsx 32 factor22 16 (var (at-offset opnd2 16));
mul 32 product1 (var factor11) (var factor21);
mul 32 product2 (var factor12) (var factor22);
movsx 64 product1 32 (var product1);
movsx 64 product2 32 (var product2);
movsx 64 addend 32 ra;
add 64 result (var product1) (var product2);
add 64 result (var result) (var addend);
mov 32 rd (var result);
movsx 64 comparator 32 (var rd);
cmpneq 64 fQF (var result) (var comparator)
end
val sem-smlal x = do
opnd1 <- rval x.opnd3;
opnd2 <- rval x.opnd4;
......
......@@ -1867,13 +1867,12 @@ val /immrotate ['rotate:2 00 0111'] = do
update@{shift={amount=imm, shifttype=ROR}}
end
val shfreg = do
shift <- query $shift;
rm <- query $rm;
return (shiftedoperand {opnd=(register rm), shift=shift})
val /rot16reg ['/rm'] = do
imm <- return (immediate (IMM5 ('10000')));
update@{shift={amount=imm, shifttype=ROR}}
end
val rotreg = do
val shfreg = do
shift <- query $shift;
rm <- query $rm;
return (shiftedoperand {opnd=(register rm), shift=shift})
......@@ -2235,7 +2234,7 @@ val / ['/cond 011 1 0 0 0 0 /rd /ra-not15 /rm 0001 /rn'] = unbitQuaternop SMLAD
### SMLADX
### - Signed Multiply Accumulate Dual Exchange
val / ['/cond 011 1 0 0 0 0 /rd /ra-not15 /rm 0011 /rn'] = unbitQuaternop SMLADX cond set0 rd ra rm rn
val / ['/cond 011 1 0 0 0 0 /rd /ra-not15 /rot16reg 0011 /rn'] = unbitQuaternop SMLADX cond set0 rd ra shfreg rn
### SMLAL
### - Signed Multiply Accumulate Long
......@@ -2413,51 +2412,51 @@ val / ['/cond 011 0 1 0 0 0 /rn /rd /shfregshtp'] = ternop PKH cond rn rd shfreg
### SXTAB
### - Signed Extend and Add Byte
val / ['/cond 011 0 1 0 1 0 /rn-not15 /rd /rotreg'] = ternop SXTAB cond rn rd rotreg
val / ['/cond 011 0 1 0 1 0 /rn-not15 /rd /rotreg'] = ternop SXTAB cond rn rd shfreg
### SXTAB16
### - Signed Extend and Add Byte 16
val / ['/cond 011 0 1 0 0 0 /rn-not15 /rd /rotreg'] = ternop SXTAB16 cond rn rd rotreg
val / ['/cond 011 0 1 0 0 0 /rn-not15 /rd /rotreg'] = ternop SXTAB16 cond rn rd shfreg
### SXTAH
### - Signed Extend and Add Halfword
val / ['/cond 011 0 1 0 1 1 /rn-not15 /rd /rotreg'] = ternop SXTAH cond rn rd rotreg
val / ['/cond 011 0 1 0 1 1 /rn-not15 /rd /rotreg'] = ternop SXTAH cond rn rd shfreg
### SXTB
### - Signed Extend Byte
val / ['/cond 011 0 1 0 1 0 1111 /rd /rotreg'] = ternop SXTB cond r15 rd rotreg
val / ['/cond 011 0 1 0 1 0 1111 /rd /rotreg'] = ternop SXTB cond r15 rd shfreg
### SXTB16
### - Signed Extend Byte 16
val / ['/cond 011 0 1 0 0 0 1111 /rd /rotreg'] = ternop SXTB16 cond r15 rd rotreg
val / ['/cond 011 0 1 0 0 0 1111 /rd /rotreg'] = ternop SXTB16 cond r15 rd shfreg
### SXTH
### - Signed Extend Halfword
val / ['/cond 011 0 1 0 1 1 1111 /rd /rotreg'] = ternop SXTH cond r15 rd rotreg
val / ['/cond 011 0 1 0 1 1 1111 /rd /rotreg'] = ternop SXTH cond r15 rd shfreg
### UXTAB
### - Unsigned Extend and Add Byte
val / ['/cond 011 0 1 1 1 0 /rn-not15 /rd /rotreg'] = ternop UXTAB cond rn rd rotreg
val / ['/cond 011 0 1 1 1 0 /rn-not15 /rd /rotreg'] = ternop UXTAB cond rn rd shfreg
### UXTAB16
### - Unsigned Extend and Add Byte 16
val / ['/cond 011 0 1 1 0 0 /rn-not15 /rd /rotreg'] = ternop UXTAB16 cond rn rd rotreg
val / ['/cond 011 0 1 1 0 0 /rn-not15 /rd /rotreg'] = ternop UXTAB16 cond rn rd shfreg
### UXTAH
### - Unsigned Extend and Add Halfword
val / ['/cond 011 0 1 1 1 1 /rn-not15 /rd /rotreg'] = ternop UXTAH cond rn rd rotreg
val / ['/cond 011 0 1 1 1 1 /rn-not15 /rd /rotreg'] = ternop UXTAH cond rn rd shfreg
### UXTB
### - Unsigned Extend Byte
val / ['/cond 011 0 1 1 1 0 1111 /rd /rotreg'] = ternop UXTB cond r15 rd rotreg
val / ['/cond 011 0 1 1 1 0 1111 /rd /rotreg'] = ternop UXTB cond r15 rd shfreg
### UXTB16
### - Unsigned Extend Byte 16
val / ['/cond 011 0 1 1 0 0 1111 /rd /rotreg'] = ternop UXTB16 cond r15 rd rotreg
val / ['/cond 011 0 1 1 0 0 1111 /rd /rotreg'] = ternop UXTB16 cond r15 rd shfreg
### UXTH
### - Unsigned Extend Halfword
val / ['/cond 011 0 1 1 1 1 1111 /rd /rotreg'] = ternop UXTH cond r15 rd rotreg
val / ['/cond 011 0 1 1 1 1 1111 /rd /rotreg'] = ternop UXTH cond r15 rd shfreg
# --- Parallel addition and Subtraction instructions ------------------
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment