Commit f45c6e96 authored by Julian Kranz's avatar Julian Kranz

X86 Specification

- Bug fixes
parent 31bbc83a
......@@ -553,11 +553,12 @@ main:
#vmaskmovdqu %xmm2, %xmm1
#vzeroall
#vzeroupper
vzeroupper
nop %rax
nop %eax
nop %ax
#nop %rax
#nop %eax
#nop %ax
#nop (%rax)
#movhlps %xmm1, %xmm2
#movlps (%rax), %xmm1
......
......@@ -287,7 +287,7 @@ val sem-neg x = do
write size dst (var temp)
end
val sem-nop x = do
val sem-nop = do
return void
end
......@@ -2663,40 +2663,41 @@ val sem-vzeroupper = do
size <- return 128;
mode64 <- mode64?;
xmm0 <- return (semantic-register-of-offset XMM0 size);
mov size xmm0 (imm 0);
xmm1 <- return (semantic-register-of-offset XMM1 size);
mov size xmm1 (imm 0);
xmm2 <- return (semantic-register-of-offset XMM2 size);
mov size xmm2 (imm 0);
xmm3 <- return (semantic-register-of-offset XMM3 size);
mov size xmm3 (imm 0);
xmm4 <- return (semantic-register-of-offset XMM4 size);
mov size xmm4 (imm 0);
xmm5 <- return (semantic-register-of-offset XMM5 size);
mov size xmm5 (imm 0);
xmm6 <- return (semantic-register-of-offset XMM6 size);
mov size xmm6 (imm 0);
xmm7 <- return (semantic-register-of-offset XMM7 size);
mov size xmm7 (imm 0);
if mode64 then do
xmm8 <- return (semantic-register-of-offset XMM8 size);
mov size xmm8 (imm 0);
xmm9 <- return (semantic-register-of-offset XMM9 size);
mov size xmm9 (imm 0);
xmm10 <- return (semantic-register-of-offset XMM10 size);
mov size xmm10 (imm 0);
xmm11 <- return (semantic-register-of-offset XMM11 size);
mov size xmm11 (imm 0);
xmm12 <- return (semantic-register-of-offset XMM12 size);
mov size xmm12 (imm 0);
xmm13 <- return (semantic-register-of-offset XMM13 size);
mov size xmm13 (imm 0);
xmm14 <- return (semantic-register-of-offset XMM14 size);
mov size xmm14 (imm 0);
xmm15 <- return (semantic-register-of-offset XMM15 size);
mov size xmm15 (imm 0)
end else
blah <- return (semantic-register-of-offset XMM0 size);
xmm0 <- return {id=Sem_XMM0,offset=size,size=size};
mov (size + blah.size) xmm0 (imm 0);
#xmm1 <- return (semantic-register-of-offset XMM1 size);
#mov size xmm1 (imm 0);
#xmm2 <- return (semantic-register-of-offset XMM2 size);
#mov size xmm2 (imm 0);
#xmm3 <- return (semantic-register-of-offset XMM3 size);
#mov size xmm3 (imm 0);
#xmm4 <- return (semantic-register-of-offset XMM4 size);
#mov size xmm4 (imm 0);
#xmm5 <- return (semantic-register-of-offset XMM5 size);
#mov size xmm5 (imm 0);
#xmm6 <- return (semantic-register-of-offset XMM6 size);
#mov size xmm6 (imm 0);
#xmm7 <- return (semantic-register-of-offset XMM7 size);
#mov size xmm7 (imm 0);
#if mode64 then do
# xmm8 <- return (semantic-register-of-offset XMM8 size);
# mov size xmm8 (imm 0);
# xmm9 <- return (semantic-register-of-offset XMM9 size);
# mov size xmm9 (imm 0);
# xmm10 <- return (semantic-register-of-offset XMM10 size);
# mov size xmm10 (imm 0);
# xmm11 <- return (semantic-register-of-offset XMM11 size);
# mov size xmm11 (imm 0);
# xmm12 <- return (semantic-register-of-offset XMM12 size);
# mov size xmm12 (imm 0);
# xmm13 <- return (semantic-register-of-offset XMM13 size);
# mov size xmm13 (imm 0);
# xmm14 <- return (semantic-register-of-offset XMM14 size);
# mov size xmm14 (imm 0);
# xmm15 <- return (semantic-register-of-offset XMM15 size);
# mov size xmm15 (imm 0)
#end else
return void
end
......
......@@ -1324,9 +1324,9 @@ val semantics insn =
| MULPS x: sem-undef-arity2 x
| MULSD x: sem-undef-arity2 x
| MULSS x: sem-undef-arity2 x
| MWAIT x: sem-nop x
| MWAIT x: sem-nop
| NEG x: sem-neg x
| NOP x: sem-nop x
| NOP x: sem-nop
| NOT x: sem-not x
| OR x: sem-or x
| ORPD x: sem-undef-arity2 x
......
......@@ -1919,6 +1919,15 @@ val ymm-rex rex reg-idx = ymm (rex ^ reg-idx)
# Deslice the mod/rm byte and put it into the the state
#reg/opcode='000',
#reg/opcode='001',
#reg/opcode='010',
#reg/opcode='011',
#reg/opcode='100',
#reg/opcode='101',
#reg/opcode='110',
#reg/opcode='111',
val /0 ['mod:2 000 rm:3'] = update @{mod=mod, rm=rm}
val /1 ['mod:2 001 rm:3'] = update @{mod=mod, rm=rm}
val /2 ['mod:2 010 rm:3'] = update @{mod=mod, rm=rm}
......@@ -4376,8 +4385,6 @@ val / [0xf7 /3]
| rexw? = unop-lock NEG r/m64
| otherwise = unop-lock NEG r/m32
### =><=
### NOP
### - No Operation
# The opcode `0x90` overlapps with `xchg` since
......@@ -4385,12 +4392,10 @@ val / [0xf7 /3]
# so we deocde 0x90 always as `xchg`
#val / [0x90] = arity0 NOP => See XCHG
#val /66 [0x90] = arity0 NOP
val /66 [0x0f 0x1f /0] = varity2 NOP r/m16 (do update @{reg/opcode='000'}; r16 end)
val / [0x0f 0x1f /0]
| opndsz? = varity2 NOP r/m16 (do update @{reg/opcode='000'}; r16 end)
| rexw? = varity2 NOP r/m64 (do update @{reg/opcode='000'}; r64 end)
| otherwise = varity2 NOP r/m32 (do update @{reg/opcode='000'}; r32 end)
#Todo: update-blah nötig? ^-
| opndsz? = varity1 NOP r/m16
| rexw? = varity1 NOP r/m64
| otherwise = varity1 NOP r/m32
### NOT
### - One's Complement Negation
......@@ -4444,11 +4449,13 @@ val /vex/0f/vexv [0x56 /r]
### OUT
### - Output to Port
val / [0xe6] = binop OUT imm8 al
val /66 [0xe7] = binop OUT imm8 ax
val / [0xe7] = binop OUT imm8 eax
val / [0xe7]
| opndsz? = binop OUT imm8 ax
| otherwise = binop OUT imm8 eax
val / [0xee] = binop OUT dx al
val /66 [0xef] = binop OUT dx ax
val / [0xef] = binop OUT dx eax
val / [0xef]
| opndsz? = binop OUT dx ax
| otherwise = binop OUT dx eax
### OUTS/OUTSB/OUTSW/OUTSD
### - Output String to Port
......@@ -4462,6 +4469,8 @@ val / [0x6f]
| opndsz? = arity0-rep OUTSW
| otherwise = arity0-rep OUTSD
### =><=
### PABSB/PABSW/PABSD
### - Packed Absolute Value
val / [0x0f 0x38 0x1c /r] = binop PABSB mm64 mm/m64
......
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