Commit d29b0c34 authored by Julian Kranz's avatar Julian Kranz

X86 RREIL Translator

- Bug fixes
parent aa8e327d
...@@ -73,7 +73,7 @@ type sem_stmts = ...@@ -73,7 +73,7 @@ type sem_stmts =
type sem_writeback = type sem_writeback =
SEM_WRITE_VAR of {size: int, id: sem_var} SEM_WRITE_VAR of {size: int, id: sem_var}
| SEM_WRITE_MEM of {size: int, address: sem_linear} | SEM_WRITE_MEM of {size: int, address: sem_linear, segment:seg_override}
val rreil-sizeOf op = val rreil-sizeOf op =
case op of case op of
......
...@@ -111,10 +111,10 @@ val segmented-lin lin sz segment = do ...@@ -111,10 +111,10 @@ val segmented-lin lin sz segment = do
real-addr-sz <- real-addr-sz; real-addr-sz <- real-addr-sz;
mode64 <- mode64?; mode64 <- mode64?;
expanded <- expand Unsigned (var lin) sz real-addr-sz; expanded <- expand Unsigned lin sz real-addr-sz;
return (segment-add mode64 expanded segment) return (segment-add mode64 expanded segment)
end end
val segmented-reg reg segment = segmented-lin reg reg.size segment val segmented-reg reg segment = segmented-lin (var reg) reg.size segment
val segmented-load dst-sz dst addr-sz address segment = do val segmented-load dst-sz dst addr-sz address segment = do
address-segmented <- segmented-lin address addr-sz segment; address-segmented <- segmented-lin address addr-sz segment;
...@@ -144,7 +144,6 @@ val segment segment = do ...@@ -144,7 +144,6 @@ val segment segment = do
return DS return DS
end end
#Todo: Für alle Größen automatische Erweiterung (Konfigurierbar auch bei read?)
val conv-with conv sz x = val conv-with conv sz x =
let let
val conv-imm conv x = case conv of val conv-imm conv x = case conv of
...@@ -191,11 +190,12 @@ val conv-with conv sz x = ...@@ -191,11 +190,12 @@ val conv-with conv sz x =
| SUM x: conv-sum conv sz x | SUM x: conv-sum conv sz x
| SCALE x: conv-scale conv sz x | SCALE x: conv-scale conv sz x
| MEM x: | MEM x:
do t <- mktemp; do
address <- conv-mem x; t <- mktemp;
segmented-load sz t x.psz address x.segment; address <- conv-mem x;
return (var t) segmented-load sz t x.psz address x.segment;
end return (var t)
end
end end
end end
...@@ -243,7 +243,7 @@ val write-offset sz x offset = ...@@ -243,7 +243,7 @@ val write-offset sz x offset =
do do
#Todo: Offset for memory operands? #Todo: Offset for memory operands?
address <- conv-with Signed x.psz x.opnd; address <- conv-with Signed x.psz x.opnd;
return (SEM_WRITE_MEM{size= x.psz,address=address}) return (SEM_WRITE_MEM{size=x.psz,address=address,segment=x.segment})
end end
| REG x: | REG x:
do do
...@@ -266,8 +266,7 @@ val commit sz a b = ...@@ -266,8 +266,7 @@ val commit sz a b =
case a of case a of
SEM_WRITE_MEM x: SEM_WRITE_MEM x:
#store x (SEM_LIN{size=sz,opnd1=b}) #store x (SEM_LIN{size=sz,opnd1=b})
#Todo: fix segment segmented-store x (SEM_LIN{size=sz,opnd1=b}) x.segment
segmented-store x (SEM_LIN{size=sz,opnd1=b}) SEG_NONE
| SEM_WRITE_VAR x: | SEM_WRITE_VAR x:
#TODO: no zero extension when not in 64bit mode #TODO: no zero extension when not in 64bit mode
case sz of case sz of
......
...@@ -647,11 +647,9 @@ type insn = ...@@ -647,11 +647,9 @@ type insn =
| CMP of arity2 | CMP of arity2
| CMPPD of arity3 | CMPPD of arity3
| CMPPS of arity3 | CMPPS of arity3
| CMPSB | CMPS of arity2
| CMPSD of varity | CMPSD of varity
| CMPSQ
| CMPSS of arity3 | CMPSS of arity3
| CMPSW
| CMPXCHG of arity2 | CMPXCHG of arity2
| CMPXCHG16B of arity1 | CMPXCHG16B of arity1
| CMPXCHG8B of arity1 | CMPXCHG8B of arity1
...@@ -1966,12 +1964,12 @@ val mem op = do ...@@ -1966,12 +1964,12 @@ val mem op = do
mode64 <- mode64?; mode64 <- mode64?;
if mode64 then if mode64 then
case r of case r of
FS: return SEG_OVERRIDE r FS: return (SEG_OVERRIDE r)
| GS: return SEG_OVERRIDE r | GS: return (SEG_OVERRIDE r)
| _: return SEG_NONE | _: return SEG_NONE
end end
else else
return SEG_OVERRIDE r return (SEG_OVERRIDE r)
end end
end end
end end
......
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