Commit d1c2faf4 authored by Julian Kranz's avatar Julian Kranz

*

- Added address to immediates
parent 5ad0c59d
...@@ -39,8 +39,8 @@ main: ...@@ -39,8 +39,8 @@ main:
#movbeq (%rax), %rbx #movbeq (%rax), %rbx
maskmovq %mm3, %mm1 #maskmovq %mm3, %mm1
vmaskmovdqu %xmm3, %xmm1 #vmaskmovdqu %xmm3, %xmm1
#loop main #loop main
#loope main #loope main
...@@ -555,9 +555,13 @@ main: ...@@ -555,9 +555,13 @@ main:
#vzeroall #vzeroall
#vzeroupper #vzeroupper
movhlps %xmm1, %xmm2 #movhlps %xmm1, %xmm2
movlps (%rax), %xmm1 #movlps (%rax), %xmm1
add $0x42, %rax
add $0x01bb, %bx
add $0x7abbccdd, %rax
#add $0xaabbccdd12345678, %rax
#pushq %rbp #pushq %rbp
.cfi_def_cfa_offset 16 .cfi_def_cfa_offset 16
......
...@@ -182,10 +182,10 @@ val show/scale s = ...@@ -182,10 +182,10 @@ val show/scale s =
val show/operand op = val show/operand op =
case op of case op of
IMM8 x: showbitvec x IMM8 x: showbitvec x.imm +++ "@" +++ showint x.address
| IMM16 x: showbitvec x | IMM16 x: showbitvec x.imm +++ "@" +++ showint x.address
| IMM32 x: showbitvec x | IMM32 x: showbitvec x.imm +++ "@" +++ showint x.address
| IMM64 x: showbitvec x | IMM64 x: showbitvec x.imm +++ "@" +++ showint x.address
| REG x: show/register x | REG x: show/register x
| MEM x: show/memsz x.sz -++ show/segment x.segment +++ "[" +++ show/operand x.opnd +++ "]" | MEM x: show/memsz x.sz -++ show/segment x.segment +++ "[" +++ show/operand x.opnd +++ "]"
| SUM x: show/operand x.a +++ "+" +++ show/operand x.b | SUM x: show/operand x.a +++ "+" +++ show/operand x.b
......
...@@ -884,7 +884,7 @@ val sem-vphsubsw x = sem-phbinop-vphbinop-opnd '1' 16 sub-signed-saturating x.op ...@@ -884,7 +884,7 @@ val sem-vphsubsw x = sem-phbinop-vphbinop-opnd '1' 16 sub-signed-saturating x.op
val sem-pinsr-vpinsr-opnd avx-encoded element-size opnd1 opnd2 opnd3 opnd4 = do val sem-pinsr-vpinsr-opnd avx-encoded element-size opnd1 opnd2 opnd3 opnd4 = do
offset <- return ( offset <- return (
case opnd4 of case opnd4 of
IMM8 x: x IMM8 x: x.imm
end end
); );
offset-mask <- return ( offset-mask <- return (
...@@ -1501,7 +1501,7 @@ val sem-pshuf-vdhwlw avx-encoded element-size low-size high-size x = do ...@@ -1501,7 +1501,7 @@ val sem-pshuf-vdhwlw avx-encoded element-size low-size high-size x = do
indices <- return ( indices <- return (
case x.opnd3 of case x.opnd3 of
IMM8 x: x IMM8 x: x.imm
end end
); );
...@@ -1632,7 +1632,7 @@ val sem-psxldq-vpsxldq-opnd avx-encoded shifter opnd1 opnd2 opnd3 = do ...@@ -1632,7 +1632,7 @@ val sem-psxldq-vpsxldq-opnd avx-encoded shifter opnd1 opnd2 opnd3 = do
amount <- return (zx ( amount <- return (zx (
case opnd3 of case opnd3 of
IMM8 x: x IMM8 x: x.imm
end end
)); ));
amount <- return ( amount <- return (
......
...@@ -175,10 +175,10 @@ val conv-with conv sz x = ...@@ -175,10 +175,10 @@ val conv-with conv sz x =
val conv-mem x = conv-with Signed x.psz x.opnd val conv-mem x = conv-with Signed x.psz x.opnd
in in
case x of case x of
IMM8 x: conv-imm conv x IMM8 x: conv-imm conv x.imm
| IMM16 x: conv-imm conv x | IMM16 x: conv-imm conv x.imm
| IMM32 x: conv-imm conv x | IMM32 x: conv-imm conv x.imm
| IMM64 x: conv-imm conv x | IMM64 x: conv-imm conv x.imm
| REG x: conv-reg conv sz x | REG x: conv-reg conv sz x
| SUM x: conv-sum conv sz x | SUM x: conv-sum conv sz x
| SCALE x: conv-scale conv sz x | SCALE x: conv-scale conv sz x
...@@ -197,10 +197,10 @@ val reads conv sz x = conv-with conv sz x ...@@ -197,10 +197,10 @@ val reads conv sz x = conv-with conv sz x
val extract-imm-unsigned imm = val extract-imm-unsigned imm =
case imm of case imm of
IMM8 x: zx x IMM8 x: zx x.imm
| IMM16 x: zx x | IMM16 x: zx x.imm
| IMM32 x: zx x | IMM32 x: zx x.imm
| IMM64 x: zx x | IMM64 x: zx x.imm
end end
val read-addr-reg x = val read-addr-reg x =
......
...@@ -600,10 +600,10 @@ type register = ...@@ -600,10 +600,10 @@ type register =
| RIP | RIP
type opnd = type opnd =
IMM8 of 8 IMM8 of {imm:8,address:int}
| IMM16 of 16 | IMM16 of {imm:16,address:int}
| IMM32 of 32 | IMM32 of {imm:32,address:int}
| IMM64 of 64 | IMM64 of {imm:64,address:int}
| REG of register | REG of register
| MEM of {sz:int,psz:int,segment:seg_override,opnd:opnd} | MEM of {sz:int,psz:int,segment:seg_override,opnd:opnd}
| SUM of {a:opnd,b:opnd} | SUM of {a:opnd,b:opnd}
...@@ -1611,11 +1611,15 @@ val ymm14 = return (REG YMM14) ...@@ -1611,11 +1611,15 @@ val ymm14 = return (REG YMM14)
val ymm15 = return (REG YMM15) val ymm15 = return (REG YMM15)
val st0 = return (REG ST0) val st0 = return (REG ST0)
val imm8 ['b:8'] = return (IMM8 b) val imm-build cons b size = do
val imm16 ['b1:8' 'b2:8'] = return (IMM16 (b2 ^ b1)) ip <- ipget;
val imm32 ['b1:8' 'b2:8' 'b3:8' 'b4:8'] = return (IMM32 (b4 ^ b3 ^ b2 ^ b1)) return (cons {imm=b,address=(ip - size)})
val imm64 ['b1:8' 'b2:8' 'b3:8' 'b4:8' 'b5:8' 'b6:8' 'b7:8' 'b8:8'] = end
return (IMM64 (b8 ^ b7 ^ b6 ^ b5 ^ b4 ^ b3 ^ b2 ^ b1))
val imm8 ['b:8'] = imm-build IMM8 b 1
val imm16 ['b1:8' 'b2:8'] = imm-build IMM16 (b2 ^ b1) 2
val imm32 ['b1:8' 'b2:8' 'b3:8' 'b4:8'] = imm-build IMM32 (b4 ^ b3 ^ b2 ^ b1) 4
val imm64 ['b1:8' 'b2:8' 'b3:8' 'b4:8' 'b5:8' 'b6:8' 'b7:8' 'b8:8'] = imm-build IMM64 (b8 ^ b7 ^ b6 ^ b5 ^ b4 ^ b3 ^ b2 ^ b1) 8
val rel8 ['b:8'] = return (REL8 b) val rel8 ['b:8'] = return (REL8 b)
val rel16 ['b1:8' 'b2:8'] = return (REL16 (b2 ^ b1)) val rel16 ['b1:8' 'b2:8'] = return (REL16 (b2 ^ b1))
...@@ -2539,7 +2543,7 @@ val far-ind cons giveOp = exception-rep-repne-lock (do ...@@ -2539,7 +2543,7 @@ val far-ind cons giveOp = exception-rep-repne-lock (do
return (cons {opnd-sz=opnd-sz,addr-sz=addr-sz,rep='0',repne='0',lock='0',opnd1=FARABS op}) return (cons {opnd-sz=opnd-sz,addr-sz=addr-sz,rep='0',repne='0',lock='0',opnd1=FARABS op})
end) end)
val one = return (IMM8 '00000001') val one = return (IMM8 {imm='00000001',address=0})
val // a = val // a =
do b <- a; do b <- a;
......
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