Commit cc3a8a7f authored by Benedikt Geßele's avatar Benedikt Geßele

jalr, jalr-hb, ldxc1, luxc1,

parent 5f5b628f
......@@ -4,6 +4,7 @@ in case i of
IMM21 i: inner i 21
| IMM32 i: inner i 32
| BP i: inner i 2
| SA2 i: inner i 2
| OFFSET23 i: inner i 23
| OFFSET28 i: inner i 28
| C2CONDITION i: inner i 5
......
......@@ -39,6 +39,7 @@ val revision/show/immediate imm =
IMM21 x: show-int (zx x)
| IMM32 x: show-int (zx x)
| BP x: show-int (zx x)
| SA2 x: show-int (zx x)
| OFFSET23 x: show-int (zx x)
| OFFSET28 x: show-int (zx x)
| C2CONDITION x: show-int (zx x)
......
......@@ -766,30 +766,6 @@ end
val sem-jalr-hb x = sem-jalr x
val sem-jr x = do
rs <- rval Signed x.op;
size <- return (sizeof-rval x.op);
pc <- return (semantic-reg-of Sem_SREG);
pc_true <- mktemp;
mov size pc_true rs;
pc_false <- mktemp;
mov size pc_false rs;
mov 1 pc_false (imm 0);
config1CA <- return (fCA);
cond <- /eq 1 (var config1CA) (imm 0);
isamode <- return (semantic-reg-of Sem_ISA_MODE);
_if (/neq 1 (var config1CA) (imm 0)) _then
mov isamode.size isamode rs;
cbranch cond (address pc.size (var pc_true)) (address pc.size (var pc_false))
end
val sem-jr-hb x = sem-jr x
val is-user-mode = do
dm <- return fDM;
ksu <- return fKSU;
......@@ -930,17 +906,6 @@ val sem-ll x = do
sem-lw x
end
val sem-lui x = do
immediate <- rval Unsigned x.op2;
size <- return (sizeof-lval x.op1);
size_imm <- return (sizeof-rval x.op2);
res <- mktemp;
shl size res immediate (imm (32-size_imm));
write x.op1 (var res)
end
val sem-madd-maddu-msub-msubu ext_op add_sub_op x = do
rs <- rval Signed x.op1;
rt <- rval Signed x.op2;
......@@ -968,8 +933,6 @@ val sem-madd-maddu-msub-msubu ext_op add_sub_op x = do
mov size hi (var (at-offset res size))
end
val sem-madd x = sem-madd-maddu-msub-msubu movsx add x
val sem-maddu x = sem-madd-maddu-msub-msubu movzx add x
val sem-msub x = sem-madd-maddu-msub-msubu movzx sub x
val sem-msubu x = sem-madd-maddu-msub-msubu movzx sub x
......@@ -1524,28 +1487,20 @@ val semantics i =
| JAL x: sem-jal x
| JALR x: sem-jalr x
| JALR-HB x: sem-jalr-hb x
| JR x: sem-jr x
| JR-HB x: sem-jr-hb x
| LB x: sem-lb x
| LBE x: sem-lb x
| LBU x: sem-lbu x
| LBUE x: sem-lbu x
| LDC1 x: sem-default-binop-lr-tuple-generic i x
| LDXC1 x: sem-default-binop-lr-tuple-generic i x
| LH x: sem-lh x
| LHE x: sem-lh x
| LHU x: sem-lhu x
| LHUE x: sem-lhu x
| LL x: sem-ll x
| LLE x: sem-ll x
| LUI x: sem-lui x
| LUXC1 x: sem-default-binop-lr-tuple-generic i x
| LW x: sem-lw x
| LWC1 x: sem-default-binop-lr-tuple-generic i x
| LWE x: sem-lw x
| MADD x: sem-madd x
| MADD-fmt x: sem-default-ternop-flrr-generic i x
| MADDU x: sem-maddu x
| MFC0 x: sem-default-ternop-lrr-generic i x
| MFC1 x: sem-default-binop-lr-generic i x
| MFC2 x: sem-default-binop-lr-generic i x
......
......@@ -41,6 +41,17 @@ end
val sem-div x = sem-div-divu divs mods x
val sem-divu x = sem-div-divu div mod x
val sem-lui x = do
immediate <- rval Unsigned x.op2;
size <- return (sizeof-lval x.op1);
size_imm <- return (sizeof-rval x.op2);
res <- mktemp;
shl size res immediate (imm (32-size_imm));
write x.op1 (var res)
end
val sem-lwl x = do
off/base <- rval Signed x.op2;
base <- return (extract-tuple off/base).opnd1;
......@@ -116,6 +127,30 @@ val sem-lwr x = do
write x.op1 (var res)
end
val sem-jr x = do
rs <- rval Signed x.op;
size <- return (sizeof-rval x.op);
pc <- return (semantic-reg-of Sem_SREG);
pc_true <- mktemp;
mov size pc_true rs;
pc_false <- mktemp;
mov size pc_false rs;
mov 1 pc_false (imm 0);
config1CA <- return (fCA);
cond <- /eq 1 (var config1CA) (imm 0);
isamode <- return (semantic-reg-of Sem_ISA_MODE);
_if (/neq 1 (var config1CA) (imm 0)) _then
mov isamode.size isamode rs;
cbranch cond (address pc.size (var pc_true)) (address pc.size (var pc_false))
end
val sem-jr-hb x = sem-jr x
val sem-jalx x = do
isamode <- return (semantic-reg-of Sem_ISA_MODE);
......@@ -124,6 +159,9 @@ val sem-jalx x = do
sem-jal x
end
val sem-madd x = sem-madd-maddu-msub-msubu movsx add x
val sem-maddu x = sem-madd-maddu-msub-msubu movzx add x
val revision/semantics i =
......@@ -154,13 +192,21 @@ val revision/semantics i =
| CVT-S-PU x: sem-default-binop-lr-generic i x
| DIV x: sem-div x
| DIVU x: sem-divu x
| JR x: sem-jr x
| JR-HB x: sem-jr-hb x
| JALX x: sem-jalx x
| LDC2 x: sem-default-binop-rr-tuple-generic i x
| LDXC1 x: sem-default-binop-lr-tuple-generic i x
| LUI x: sem-lui x
| LUXC1 x: sem-default-binop-lr-tuple-generic i x
| LWC2 x: sem-default-binop-rr-tuple-generic i x
| LWL x: sem-lwl x
| LWLE x: sem-lwl x
| LWR x: sem-lwr x
| LWRE x: sem-lwr x
| LWXC1 x: sem-default-binop-lr-tuple-generic i x
| MADD x: sem-madd x
| MADD-fmt x: sem-default-ternop-flrr-generic i x
| MADDU x: sem-maddu x
| SDC2 x: sem-default-binop-rr-tuple-generic i x
end
......@@ -3,6 +3,7 @@ val revision/sizeof-imm imm =
IMM21 i: 21
| IMM32 i: 32
| BP i: 2
| SA2 i: 2
| OFFSET23 i: 23
| OFFSET28 i: 28
| C2CONDITION i: 5
......@@ -19,6 +20,7 @@ in
IMM21 i: from-vec sn i
| IMM32 i: from-vec sn i
| BP i: from-vec sn i
| SA2 i: from-vec sn i
| OFFSET23 i: from-vec sn i
| OFFSET28 i: from-vec sn i
| C2CONDITION i: from-vec sn i
......@@ -262,6 +264,21 @@ val sem-jic x = do
jump (address size (var pc_new))
end
val sem-lsa x = do
rs <- rval Signed x.op2;
rt <- rval Signed x.op3;
sa2 <- rval Signed x.op4;
size <- return (sizeof-lval x.op1);
sa <- return (1 + lin-to-int sa2);
res <- mktemp;
shl size res rs (imm sa);
add size res (var res) rt;
write x.op1 (var res)
end
val revision/semantics i =
case i of
ADDIUPC x: sem-addiupc x
......@@ -306,4 +323,11 @@ val revision/semantics i =
| EVP x: sem-default-unop-l-generic i x
| JIALC x: sem-jialc x
| JIC x: sem-jic x
| LSA x: sem-lsa x
| MADDF-fmt x: sem-default-ternop-flrr-generic i x
| MSUBF-fmt x: sem-default-ternop-flrr-generic i x
| MAX-fmt x: sem-default-ternop-flrr-generic i x
| MAXA-fmt x: sem-default-ternop-flrr-generic i x
| MIN-fmt x: sem-default-ternop-flrr-generic i x
| MINA-fmt x: sem-default-ternop-flrr-generic i x
end
......@@ -72,28 +72,20 @@ val traverse f insn =
| JAL x: f "JAL" (UNOP_R x)
| JALR x: f "JALR" (BINOP_LR x)
| JALR-HB x: f "JALR.HB" (BINOP_LR x)
| JR x: f "JR" (UNOP_R x)
| JR-HB x: f "JR.HB" (UNOP_R x)
| LB x: f "LB" (BINOP_LR x)
| LBE x: f "LBE" (BINOP_LR x)
| LBU x: f "LBU" (BINOP_LR x)
| LBUE x: f "LBUE" (BINOP_LR x)
| LDC1 x: f "LDC1" (BINOP_LR x)
| LDXC1 x: f "LDXC1" (BINOP_LR x)
| LH x: f "LH" (BINOP_LR x)
| LHE x: f "LHE" (BINOP_LR x)
| LHU x: f "LHU" (BINOP_LR x)
| LHUE x: f "LHUE" (BINOP_LR x)
| LL x: f "LL" (BINOP_LR x)
| LLE x: f "LLE" (BINOP_LR x)
| LUI x: f "LUI" (BINOP_LR x)
| LUXC1 x: f "LUXC1" (BINOP_LR x)
| LW x: f "LW" (BINOP_LR x)
| LWC1 x: f "LWC1" (BINOP_LR x)
| LWE x: f "LWE" (BINOP_LR x)
| MADD x: f "MADD" (BINOP_RR x)
| MADD-fmt x: f "MADD" (QUADOP_FLRRR x)
| MADDU x: f "MADDU" (BINOP_RR x)
| MFC0 x: f "MFC0" (TERNOP_LRR x)
| MFC1 x: f "MFC1" (BINOP_LR x)
| MFC2 x: f "MFC2" (BINOP_LR x)
......
......@@ -26,13 +26,21 @@ val revision/traverse f insn =
| CVT-S-PU x: f "CVT.S.PU" (BINOP_LR x)
| DIV x: f "DIV" (BINOP_RR x)
| DIVU x: f "DIVU" (BINOP_RR x)
| JR x: f "JR" (UNOP_R x)
| JR-HB x: f "JR.HB" (UNOP_R x)
| JALX x: f "JALX" (UNOP_R x)
| LDC2 x: f "LDC2" (BINOP_RR x)
| LDXC1 x: f "LDXC1" (BINOP_LR x)
| LUI x: f "LUI" (BINOP_LR x)
| LUXC1 x: f "LUXC1" (BINOP_LR x)
| LWC2 x: f "LWC2" (BINOP_RR x)
| LWL x: f "LWL" (BINOP_LR x)
| LWLE x: f "LWLE" (BINOP_LR x)
| LWR x: f "LWR" (BINOP_LR x)
| LWRE x: f "LWRE" (BINOP_LR x)
| LWXC1 x: f "LWXC1" (BINOP_LR x)
| MADD x: f "MADD" (BINOP_RR x)
| MADD-fmt x: f "MADD" (QUADOP_FLRRR x)
| MADDU x: f "MADDU" (BINOP_RR x)
| SDC2 x: f "SDC2" (BINOP_RR x)
end
......@@ -42,4 +42,11 @@ val revision/traverse f insn =
| EVP x: f "EVP" (UNOP_L x)
| JIALC x: f "JIALC" (BINOP_RR x)
| JIC x: f "JIC" (BINOP_RR x)
| LSA x: f "LSA" (QUADOP_LRRR x)
| MADDF-fmt x: f "MADDF" (TERNOP_FLRR x)
| MSUBF-fmt x: f "MSUBF" (TERNOP_FLRR x)
| MAX-fmt x: f "MAX" (TERNOP_FLRR x)
| MAXA-fmt x: f "MAXA" (TERNOP_FLRR x)
| MIN-fmt x: f "MIN" (TERNOP_FLRR x)
| MINA-fmt x: f "MINA" (TERNOP_FLRR x)
end
......@@ -328,14 +328,6 @@ val / ['000000 /rs 00000 /rd 1 0000 001001']
| jalr? = binop JALR-HB rd (right rs)
| otherwise = nullop UNPREDICTABLE
### JR
### - Jump Register
val / ['000000 /rs 0000000000 00000 001000'] = unop JR (right rs)
### JR-HB
### - Jump Register with Hazard Barrier
val / ['000000 /rs 0000000000 1 0000 001000'] = unop JR-HB (right rs)
### LB
### - Load Byte
val / ['100000 /base /rt /offset16'] = binop LB rt offset16/base
......@@ -360,10 +352,6 @@ val / ['011111 /base /rt /offset9 0 101000']
### - Load Doubleword to Floating Point
val / ['110101 /base /ft /offset16'] = binop LDC1 ft offset16/base
### LDXC1
### - Load Doubleword Indexed to Floating Point
val / ['010011 /base /index 00000 /fd 000001'] = binop LDXC1 fd index/base
### LH
### - Load Halfword
val / ['100001 /base /rt /offset16'] = binop LH rt offset16/base
......@@ -394,10 +382,6 @@ val / ['011111 /base /rt /offset9 0 101110']
| asmode? = nullop UNDEFINED
| otherwise = binop LLE rt offset9/base
### LUXC1
### - Load Doubleword Indexed Unaligned to Floating Point
val / ['010011 /base /index 00000 /fd 000101'] = binop LUXC1 fd index/base
### LW
### - Load word
val / ['100011 /base /rt /offset16'] = binop LW rt offset16/base
......@@ -412,18 +396,6 @@ val / ['011111 /base /rt /offset9 0 101111']
| asmode? = nullop UNDEFINED
| otherwise = binop LWE rt offset9/base
### MADD
### - Multiply and Add Word to Hi,Lo
val / ['011100 /rs /rt 00000 00000 000000'] = binop MADD (right rs) (right rt)
### MADD-fmt
### - Floating Point Multiply Add
val / ['010011 /fr /ft /fs /fd 100 /fmt3sdps'] = quadop-fmt MADD-fmt fmt fd (right fr) (right fs) (right ft)
### MADDU
### - Multiply and Add Unsigned Word to Hi,Lo
val / ['011100 /rs /rt 00000 00000 000001'] = binop MADDU (right rs) (right rt)
### MFC0
### - Move from Coprocessor 0
val / ['010000 00000 /rt /rd 00000000 /sel'] = ternop MFC0 rt rd/imm sel
......@@ -1286,28 +1258,20 @@ type instruction =
| JAL of unop-r
| JALR of binop-lr
| JALR-HB of binop-lr
| JR of unop-r
| JR-HB of unop-r
| LB of binop-lr
| LBE of binop-lr
| LBU of binop-lr
| LBUE of binop-lr
| LDC1 of binop-lr
| LDXC1 of binop-lr
| LH of binop-lr
| LHE of binop-lr
| LHU of binop-lr
| LHUE of binop-lr
| LL of binop-lr
| LLE of binop-lr
| LUI of binop-lr
| LUXC1 of binop-lr
| LW of binop-lr
| LWC1 of binop-lr
| LWE of binop-lr
| MADD of binop-rr
| MADD-fmt of quadop-flrrr
| MADDU of binop-rr
| MFC0 of ternop-lrr
| MFC1 of binop-lr
| MFC2 of binop-lr
......
......@@ -131,6 +131,14 @@ val / ['000000 /rs /rt 0000000000 011010'] = binop DIV (right rs) (right rt)
### - Divide Unsigned Word
val / ['000000 /rs /rt 0000000000 011011'] = binop DIVU (right rs) (right rt)
### JR
### - Jump Register
val / ['000000 /rs 0000000000 00000 001000'] = unop JR (right rs)
### JR-HB
### - Jump Register with Hazard Barrier
val / ['000000 /rs 0000000000 1 0000 001000'] = unop JR-HB (right rs)
### JALX
### - Jump and Link Exchange
val / ['011101 /instr_index'] = unop JALX instr_index
......@@ -139,10 +147,18 @@ val / ['011101 /instr_index'] = unop JALX instr_index
### - Load Doubleword to Coprocessor 2
val / ['110110 /base /rt /offset16'] = binop LDC2 rt/imm offset16/base
### LDXC1
### - Load Doubleword Indexed to Floating Point
val / ['010011 /base /index 00000 /fd 000001'] = binop LDXC1 fd index/base
### LUI
### - Load Upper Immediate
val / ['001111 00000 /rt /immediate16'] = binop LUI rt immediate16
### LUXC1
### - Load Doubleword Indexed Unaligned to Floating Point
val / ['010011 /base /index 00000 /fd 000101'] = binop LUXC1 fd index/base
### LWC2
### - Load Word to Coprocessor 2
val / ['110010 /base /rt /offset16'] = binop LWC2 rt/imm offset16/base
......@@ -171,6 +187,18 @@ val / ['011111 /base /rt /offset9 0 011010']
### - Load Word Indexed to Floating Point
val / ['010011 /base /index 00000 /fd 000000'] = binop LWXC1 fd index/base
### MADD
### - Multiply and Add Word to Hi,Lo
val / ['011100 /rs /rt 00000 00000 000000'] = binop MADD (right rs) (right rt)
### MADD-fmt
### - Floating Point Multiply Add
val / ['010011 /fr /ft /fs /fd 100 /fmt3sdps'] = quadop-fmt MADD-fmt fmt fd (right fr) (right fs) (right ft)
### MADDU
### - Multiply and Add Unsigned Word to Hi,Lo
val / ['011100 /rs /rt 00000 00000 000001'] = binop MADDU (right rs) (right rt)
### SDC2
### - Store Doubleword from Coprocessor 2
val / ['111110 /base /rt /offset16'] = binop SDC2 rt/imm offset16/base
......@@ -207,14 +235,22 @@ type instruction =
| CVT-S-PU of binop-lr
| DIV of binop-rr
| DIVU of binop-rr
| JR of unop-r
| JR-HB of unop-r
| JALX of unop-r
| LDC2 of binop-rr
| LDXC1 of binop-lr
| LUI of binop-lr
| LUXC1 of binop-lr
| LWC2 of binop-rr
| LWL of binop-lr
| LWLE of binop-lr
| LWR of binop-lr
| LWRE of binop-lr
| LWXC1 of binop-lr
| MADD of binop-rr
| MADD-fmt of quadop-flrrr
| MADDU of binop-rr
| SDC2 of binop-rr
type format =
......
......@@ -6,7 +6,6 @@
# guard conditions
####
val lui? s = (s.rs == '00000')
val bgtz? s = (s.rt == '00000')
val bgtzalc? s = (s.rs == '00000') and (not (s.rt == '00000'))
val bgezalc? s = (s.rs == s.rt) and (not (s.rs == '00000'))
......@@ -55,9 +54,7 @@ val / ['111011 /rs 11111 /immediate16'] = binop ALUIPC rs immediate32
### AUI
### - Add Immediate to Upper Bits
val / ['001111 /rs /rt /immediate16']
| lui? = binop LUI rt immediate16
| otherwise = ternop AUI rt (right rs) immediate32
val / ['001111 /rs /rt /immediate16'] = ternop AUI rt (right rs) immediate32
### AUIPC
### - Add Upper Immediate to PC
......@@ -207,6 +204,14 @@ val / ['010000 01011 /rt 00000 00000 1 00 100'] = unop DVP rt
### - Enable Virtual Processor
val / ['010000 01011 /rt 00000 00000 0 00 100'] = unop EVP rt
### JR
### Jump Register
### => see JALR with rd = 0
### JR-HB
### Jump Register with Hazard Barrier
### => see JALR-HB with rd = 0
### JIALC
### - Jump Indexed and Link, Compact
val / ['111110 00000 /rt /offset16'] = binop JIALC (right rt) offset16
......@@ -215,10 +220,38 @@ val / ['111110 00000 /rt /offset16'] = binop JIALC (right rt) offset16
### - Jump Indexed and Link, Compact
val / ['110110 00000 /rt /offset16'] = binop JIALC (right rt) offset16
### LSA
### - Load Scaled Address
val / ['000000 /rs /rt /rd 000 /sa2 000101'] = quadop LSA rd (right rs) (right rt) sa2
### LUI
### - Load Upper Immediate
### => see AUI r0, rt, immediate16
### MADDF-fmt
### - Floating Point Fused Multiply Add
val / ['010001 /fmt5sd /ft /fs /fd 011000'] = ternop-fmt MADDF-fmt fmt fd (right fs) (right ft)
### MSUBF-fmt
### - Floating Point Fused Multiply Subtract
val / ['010001 /fmt5sd /ft /fs /fd 011001'] = ternop-fmt MSUBF-fmt fmt fd (right fs) (right ft)
### MAX-fmt
### - Scalar Floating-Point Max
val / ['010001 /fmt5sd /ft /fs /fd 011110'] = ternop-fmt MAX-fmt fmt fd (right fs) (right ft)
### MAXA-fmt
### - Scalar Floating-Point maxNumMag
val / ['010001 /fmt5sd /ft /fs /fd 011111'] = ternop-fmt MAXA-fmt fmt fd (right fs) (right ft)
### MIN-fmt
### - Scalar Floating-Point Min
val / ['010001 /fmt5sd /ft /fs /fd 011100'] = ternop-fmt MIN-fmt fmt fd (right fs) (right ft)
### MINA-fmt
### - Scalar Floating-Point minNumMag
val / ['010001 /fmt5sd /ft /fs /fd 011101'] = ternop-fmt MINA-fmt fmt fd (right fs) (right ft)
type instruction =
ADDIUPC of binop-lr
......@@ -263,11 +296,20 @@ type instruction =
| EVP of unop-l
| JIALC of binop-rr
| JIC of binop-rr
| LSA of quadop-lrrr
| MADDF-fmt of ternop-flrr
| MSUBF-fmt of ternop-flrr
| MAX-fmt of ternop-flrr
| MAXA-fmt of ternop-flrr
| MIN-fmt of ternop-flrr
| MINA-fmt of ternop-flrr
type imm =
IMM21 of 21
| IMM32 of 32
| BP of 2
| SA2 of 2
| OFFSET23 of 23
| OFFSET28 of 28
| C2CONDITION of 5
......@@ -281,6 +323,7 @@ val /immediate19 ['immediate19:19'] = update@{immediate19=immediate19}
val /offset21 ['offset21:21'] = update@{offset21=offset21}
val /offset26 ['offset26:26'] = update@{offset26=offset26}
val /bp ['bp:2'] = update@{bp=bp}
val /sa2 ['sa2:2'] = update@{sa2=sa2}
val /ct ['ct:5'] = update@{ct=ct}
val /fmt5sd/wl ['10100'] = update@{fmt=S}
val /fmt5sd/wl ['10101'] = update@{fmt=D}
......@@ -316,6 +359,11 @@ val bp = do
return (IMM (BP bp))
end
val sa2 = do
sa2 <- query $sa2;
return (IMM (SA2 sa2))
end
val condn = do
condn <- query $condn;
return (condn-from-bits (condn))
......
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