Commit c4c78d78 authored by Benedikt Geßele's avatar Benedikt Geßele

mips dvp, evp, jialc,jalx

parent 6454045a
......@@ -153,6 +153,16 @@ val sem-default-nullop-generic insn = do
prim-generic (mnemonic-of insn) varls-none varls-none
end
val sem-default-unop-l-generic insn x = do
dst-sz <- return (sizeof-lval x.op);
dst <- lval Signed x.op;
dst-up <- unpack-lin dst-sz dst;
prim-generic (mnemonic-of insn) varls-none (varls-one (varl dst-sz dst-up))
end
val sem-default-unop-r-tuple-generic insn x = do
src1-sz <- return (sizeof-rval x.op);
src2-sz <- return (sizeof-rval x.op);
......@@ -756,14 +766,6 @@ end
val sem-jalr-hb x = sem-jalr x
val sem-jalx x = do
isamode <- return (semantic-reg-of Sem_ISA_MODE);
xorb 1 isamode (var isamode) (imm 1);
sem-jal x
end
val sem-jr x = do
rs <- rval Signed x.op;
size <- return (sizeof-rval x.op);
......@@ -1522,7 +1524,6 @@ val semantics i =
| JAL x: sem-jal x
| JALR x: sem-jalr x
| JALR-HB x: sem-jalr-hb x
| JALX x: sem-jalx x
| JR x: sem-jr x
| JR-HB x: sem-jr-hb x
| LB x: sem-lb x
......
......@@ -116,6 +116,14 @@ val sem-lwr x = do
write x.op1 (var res)
end
val sem-jalx x = do
isamode <- return (semantic-reg-of Sem_ISA_MODE);
xorb 1 isamode (var isamode) (imm 1);
sem-jal x
end
val revision/semantics i =
......@@ -146,6 +154,7 @@ val revision/semantics i =
| CVT-S-PU x: sem-default-binop-lr-generic i x
| DIV x: sem-div x
| DIVU x: sem-divu x
| JALX x: sem-jalx x
| LDC2 x: sem-default-binop-rr-tuple-generic i x
| LWC2 x: sem-default-binop-rr-tuple-generic i x
| LWL x: sem-lwl x
......
......@@ -232,6 +232,22 @@ val sem-divu x = sem-div-divu-mod-modu div x
val sem-mod x = sem-div-divu-mod-modu mods x
val sem-modu x = sem-div-divu-mod-modu mod x
val sem-jialc x = do
rt <- rval Signed x.op1;
off <- rval Signed x.op2;
size <- return (sizeof-rval x.op1);
pc <- return (semantic-reg-of Sem_SREG);
ra <- return (semantic-gpr-of RA);
pc_new <- mktemp;
mov size pc_new rt;
add size pc_new (var pc_new) off;
mov size ra (var pc_new);
jump (address size (var pc_new))
end
val revision/semantics i =
case i of
ADDIUPC x: sem-addiupc x
......@@ -272,4 +288,7 @@ val revision/semantics i =
| MOD x: sem-mod x
| DIVU x: sem-divu x
| MODU x: sem-modu x
| DVP x: sem-default-unop-l-generic i x
| EVP x: sem-default-unop-l-generic i x
| JIALC x: sem-jialc x
end
......@@ -72,7 +72,6 @@ val traverse f insn =
| JAL x: f "JAL" (UNOP_R x)
| JALR x: f "JALR" (BINOP_LR x)
| JALR-HB x: f "JALR.HB" (BINOP_LR x)
| JALX x: f "JALX" (UNOP_R x)
| JR x: f "JR" (UNOP_R x)
| JR-HB x: f "JR.HB" (UNOP_R x)
| LB x: f "LB" (BINOP_LR x)
......
......@@ -26,6 +26,7 @@ val revision/traverse f insn =
| CVT-S-PU x: f "CVT.S.PU" (BINOP_LR x)
| DIV x: f "DIV" (BINOP_RR x)
| DIVU x: f "DIVU" (BINOP_RR x)
| JALX x: f "JALX" (UNOP_R x)
| LDC2 x: f "LDC2" (BINOP_RR x)
| LWC2 x: f "LWC2" (BINOP_RR x)
| LWL x: f "LWL" (BINOP_LR x)
......
......@@ -38,4 +38,7 @@ val revision/traverse f insn =
| MOD x: f "MOD" (TERNOP_LRR x)
| DIVU x: f "DIVU" (TERNOP_LRR x)
| MODU x: f "MODU" (TERNOP_LRR x)
| DVP x: f "DVP" (UNOP_L x)
| EVP x: f "EVP" (UNOP_L x)
| JIALC x: f "JIALC" (BINOP_RR x)
end
......@@ -328,10 +328,6 @@ val / ['000000 /rs 00000 /rd 1 0000 001001']
| jalr? = binop JALR-HB rd (right rs)
| otherwise = nullop UNPREDICTABLE
### JALX
### - Jump and Link Exchange
val / ['011101 /instr_index'] = unop JALX instr_index
### JR
### - Jump Register
val / ['000000 /rs 0000000000 00000 001000'] = unop JR (right rs)
......@@ -1290,7 +1286,6 @@ type instruction =
| JAL of unop-r
| JALR of binop-lr
| JALR-HB of binop-lr
| JALX of unop-r
| JR of unop-r
| JR-HB of unop-r
| LB of binop-lr
......
......@@ -131,6 +131,10 @@ val / ['000000 /rs /rt 0000000000 011010'] = binop DIV (right rs) (right rt)
### - Divide Unsigned Word
val / ['000000 /rs /rt 0000000000 011011'] = binop DIVU (right rs) (right rt)
### JALX
### - Jump and Link Exchange
val / ['011101 /instr_index'] = unop JALX instr_index
### LDC2
### - Load Doubleword to Coprocessor 2
val / ['110110 /base /rt /offset16'] = binop LDC2 rt/imm offset16/base
......@@ -203,6 +207,7 @@ type instruction =
| CVT-S-PU of binop-lr
| DIV of binop-rr
| DIVU of binop-rr
| JALX of unop-r
| LDC2 of binop-rr
| LWC2 of binop-rr
| LWL of binop-lr
......
......@@ -26,7 +26,6 @@ val bltuc? s = (not (s.rs == s.rt)) and (not (s.rs == '00000')) and (not (s.rt =
val beqc? s = ((zx s.rs) < (zx s.rt)) and (not (s.rs == '00000')) and (not (s.rt == '00000'))
val bnec? s = ((zx s.rs) < (zx s.rt)) and (not (s.rs == '00000')) and (not (s.rt == '00000'))
val beqzc? s = not (s.rs == '00000')
val bnezc? s = not (s.rs == '00000')
val bovc? s = ((zx s.rs) >= (zx s.rt))
val bnvc? s = ((zx s.rs) >= (zx s.rt))
......@@ -156,12 +155,11 @@ val / ['110110 /rs /offset21']
| beqzc? = binop BEQZC (right rs) offset23
### BNEZC
val / ['111110 /rs /offset21']
| bnezc? = binop BNEZC (right rs) offset23
val / ['111110 /rs-notnull /offset21'] = binop BNEZC (right rs) offset23
### BITSWAP
### - Swaps (reverses) bits in each byte
val / ['011111 00000 /rt /rd 00000 100000'] = binop BITSWAP rd (right rt)
val / ['011111 00000 /rt /rd 00000 100000'] = binop BITSWAP rd (right rt)
### BOVC
### - Swaps (reverses) bits in each byte
......@@ -203,6 +201,18 @@ val / ['000000 /rs /rt /rd 00010 011011'] = ternop DIVU rd (right rs) (right rt)
### MODU
val / ['000000 /rs /rt /rd 00011 011011'] = ternop MODU rd (right rs) (right rt)
### DVP
### - Disable Virtual Processor
val / ['010000 01011 /rt 00000 00000 1 00 100'] = unop DVP rt
### EVP
### - Enable Virtual Processor
val / ['010000 01011 /rt 00000 00000 0 00 100'] = unop EVP rt
### JIALC
### - Jump Indexed and Link, Compact
val / ['111110 00000 /rt /offset16'] = binop JIALC (right rt) offset16
### LUI
### - Load Upper Immediate
### => see AUI r0, rt, immediate16
......@@ -247,6 +257,9 @@ type instruction =
| MOD of ternop-lrr
| DIVU of ternop-lrr
| MODU of ternop-lrr
| DVP of unop-l
| EVP of unop-l
| JIALC of binop-rr
type imm =
IMM21 of 21
......@@ -269,6 +282,7 @@ val /ct ['ct:5'] = update@{ct=ct}
val /fmt5sd/wl ['10100'] = update@{fmt=S}
val /fmt5sd/wl ['10101'] = update@{fmt=D}
val /condn ['condn:5'] = update@{condn=condn}
val /rs-notnull ['rs@00001|00010|00011|00100|00101|00110|00111|01000|01001|01010|01011|01100|01101|01110|01111|10000|10001|10010|10011|10100|10101|10110|10111|11000|11001|11010|11011|11100|11101|11110|11111'] = update@{rs=rs}
###########################
......
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