Commit 8cca20f1 authored by Julian Kranz's avatar Julian Kranz

X86 RREIL Translator

- Added semantics of: (V)PSLLDQ
parent f608d693
......@@ -373,13 +373,16 @@ main:
#pshufw $0x2d, %mm1, %mm2
psignb %mm1, %mm2
psignb %xmm1, %xmm2
psignw %xmm1, %xmm2
psignd (%rax), %xmm2
vpsignb %xmm1, %xmm2, %xmm3
vpsignw %xmm1, %xmm2, %xmm3
vpsignd %xmm1, %xmm2, %xmm3
#psignb %mm1, %mm2
#psignb %xmm1, %xmm2
#psignw %xmm1, %xmm2
#psignd (%rax), %xmm2
#vpsignb %xmm1, %xmm2, %xmm3
#vpsignw %xmm1, %xmm2, %xmm3
#vpsignd %xmm1, %xmm2, %xmm3
pslldq $73, %xmm1
vpslldq $5, %xmm1, %xmm2
#vmovd %xmm5, %ebx
......
......@@ -1637,6 +1637,32 @@ end
val sem-psign element-size x = sem-psign-vpsign-opnd '0' element-size x.opnd1 x.opnd1 x.opnd2
val sem-vpsign element-size x = sem-psign-vpsign-opnd '1' element-size x.opnd1 x.opnd2 x.opnd3
val sem-pslldq-vpslldq-opnd avx-encoded opnd1 opnd2 opnd3 = do
size <- sizeof1 opnd1;
src <- read size opnd2;
dst <- lval size opnd1;
amount <- return (zx (
case opnd3 of
IMM8 x: x
end
));
amount <- return (
if (amount > 15) then
(16*8)
else
(amount*8)
);
temp <- mktemp;
shr size temp src (imm amount);
write-extend avx-encoded size dst (var temp)
end
val sem-pslldq x = sem-pslldq-vpslldq-opnd '0' x.opnd1 x.opnd1 x.opnd2
val sem-vpslldq x = sem-pslldq-vpslldq-opnd '1' x.opnd1 x.opnd2 x.opnd3
val ps-push opnd-sz opnd = do
mode64 <- mode64?;
stack-addr-sz <- runtime-stack-address-size;
......
......@@ -1423,7 +1423,7 @@ val semantics insn =
| PSIGND x: sem-psign 32 x
| PSIGNW x: sem-psign 16 x
| PSLLD x: sem-undef-arity2 x
| PSLLDQ x: sem-undef-arity2 x
| PSLLDQ x: sem-pslldq x
| PSLLQ x: sem-undef-arity2 x
| PSLLW x: sem-undef-arity2 x
| PSRAD x: sem-undef-arity2 x
......@@ -2066,7 +2066,10 @@ val semantics insn =
VA3 x: sem-vpsign 16 x
end
| VPSLLD x: sem-undef-varity x
| VPSLLDQ x: sem-undef-varity x
| VPSLLDQ v:
case v of
VA3 x: sem-vpslldq x
end
| VPSLLQ x: sem-undef-varity x
| VPSLLW x: sem-undef-varity x
| VPSRAD x: sem-undef-varity x
......
......@@ -4978,7 +4978,7 @@ val /vex/66/0f/38/vexv [0x0a /r] | vex128? = varity3 VPSIGND xmm128 v/xmm xmm/m1
### PSLLDQ
### - Shift Double Quadword Left Logical
val /66 [0x0f 0x73 /7-reg] = binop PSLLDQ xmm/reg128 imm8
val /vex/66/0f [0x73 /7-reg] | vndd? & vex128? = varity3 VPSLLDQ v/xmm xmm/reg128 imm8
val /vex/66/0f/vexv [0x73 /7-reg] | vndd? & vex128? = varity3 VPSLLDQ v/xmm xmm/reg128 imm8
### PSLLW/PSLLD/PSLLQ
### - Shift Packed Data Left Logical
......
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